Explicitly Parallel Instruction Computing (EPIC) technology breaks through the sequential nature of conventional processor architectures by allowing the software to communicate explicit to the processor when operations can be done in parallel. For this, it uses tighter coupling between the complier and the processor. It enables the complier to extract maximum parallelism in the original code and explicitly describe it to the processor.
For this, EPIC processors use the following three key techniques -
Explicit parallelism. Epic technology breaks through the sequential nature of today's conventional processor architectures by allowing the software to communicate explicitly to the processor when the system can perform an operation in parallel. For this, it uses tighter coupling between complier and processor. It enables the complier to extract maximum parallelism in original code and explicitly describe it to the processor. At compile time, the compiler detects which of the instructions can the system execute in parallel. It then reorders them and groups them in such a way that the system can execute instruction belonging to separate groups in parallel. At runtime, the processor exploits this explicit parallelism information provided by the compiler to execute the instructions faster.
Predication. Predication technique improves performance by reducing the number of branches and branch mispredicted. Once again, the system first takes the help of complier to reorder the instructions to reduce the number of branches as much as possible at compile time. Conventional processors are "branch prediction" technique in which the processor predicts which way a branch will fork and speculatively executes instructions along the predicted path. At the time of execution of the branch instruction, if the system finds the prediction to be correct, the processor gains performance improvement because instructions lying in the path to be executed now have already been executed and the processor can use their results directly. However, if the system finds the prediction to be wrong, it discards the results of execution of the predicted path and takes up the instructions of the correct path for execution.
However, EPIC technology uses "branch prediction" instead of "branch prediction". In this technique, instead of predicting and executing one of the paths of a branch, the processor executes instructions of all the paths of the branch exploiting as much parallelism as possible. Now when the processor discovers the actual branch outcome, it retains the valid results and discards other results. Thus, branch predication effectively removes the negative affect of branch prediction technique in cases of branch mispredicted.
Speculation. Speculation technique improves performance by reducing the effect of memory-to-processor speed mismatch. Memory access speed is much slower than processor speed. Speculative data loading technique takes care of this by loading a piece of data and keeping it ready before the processor actually requires it. It not only allows the processor to load a piece of data from memory before a program actually needs it, but it also postpones the reporting of exceptions if the loaded data is illegal.
We can also implement speculation technique by taking help of compiler. For this, the compiler analyses a program at compile time, looking for any instructions that will need data from memory. It inserts speculative load instructions in the instructions stream of the program well ahead of the instructions that need data from memory memory. It also inserts a matching speculative check instruction immediately before the instructions that need data from memory. It now reorders the surrounding instructions so that the processor can dispatch them in parallel. Now when the processor encounters a speculative load instruction at runtime, it retrieves and loads the data from memory. When the processor encounters the speculative check instruction, it verifies the load before allowing the program to use the loaded data in the next instruction. If the load is invalid, the processor does not immediately report an exception. It postpones exception reporting until it encounters a check instruction that matches the speculative load. If the load is valid, the system behaves as if the exception never happened.
Speculation technique combined with prediction technique gives the compiler flexibility to reorder instructions and increase parallelism.